library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PS2shreg is
  port(clk, serial_in : in std_logic;
       KC_current : out std_logic_vector(7 downto 0);
		 KC_last : out std_logic_vector(7 downto 0);
		 KC_third : out std_logic_vector(7 downto 0)); --horizontal: 19 downto 10, --vertical: 9 downto 0);
end PS2shreg;

architecture shift of PS2shreg is

signal shift_register : std_logic_vector (32 downto 0);

begin
	process (clk)
		variable n : integer:=0;
	begin
	
		if (rising_edge(clk)) then
--			if(n=10)
--			then
--				if (keyCode /= shift_register)
--				then
--					keyCode <= shift_register;
--				end if;
--				n := 0;
--			else
--				n := n +1;
--			end if;
			
			shift_register <= serial_in & shift_register(32 downto 1);
		end if;
		KC_current <= shift_register(31 downto 24);
		KC_last <= shift_register(20 downto 13);
		KC_third <= shift_register(9 downto 2);
	end process;

end architecture shift;